1. Field of the Invention
The present invention is directed toward a method for improving disk input/output operations within computer systems, and more particularly, to a method for performing disk operations utilizing a posted read technique and address range protection.
2. Description of the Related Art
Personal computer systems have developed over the years and new uses for them are being discovered daily. The uses are varied and, as a result, have different requirements for various subsystems forming a complete computer system. With the increased performance of computer systems, it became apparent that mass storage subsystems, such as fixed disk drives, played an increasingly important role in the transfer of data to and from the computer system.
In the past few years, a new trend in storage subsystems has emerged for improving data transfer performance, capacity and reliability. This is generally known as a disk array subsystem. One reason for building a disk array subsystem is to create a logical device that has a very high data transfer rate. This may be accomplished by "ganging" multiple standard disk drives together and transferring data to or from these drives to the system memory. If n drives are ganged together, then the effective data transfer rate is increased up to n times. This technique, known as striping, originated in the supercomputing environment where the transfer of large amounts of data to and from secondary storage is a frequent requirement. With this approach, the n physical drives become a single logical device and may be implemented either through software or hardware.
A number of reference articles on the design of disk arrays have been published in recent years. These include "Some Design Issues of Disk Arrays" by Spencer Ng, April, 1989 IEEE; "Disk Array Subsystems" by Was E. Meador, April, 1989 IEEE; and "A Case for Redundant Arrays of Inexpensive Disks (RAID)" by D. Patterson, G. Gibson and R. Catts, Report No. UCB/CSD 87/931, December 1987, Computer Science Division, University of California, Berkeley, Calif.
In general, these previous techniques have used several controller boards which could access multiple drives over a small computer system interface (SCSI). Multiple SCSI controller boards were used with multiple drives connected to each controller board. Software resident in the host computer itself performed the operation of the data distribution and control of the various controller boards and of the specific drives on a given controller board. While high disk transfer rates could be developed, the host computer was still tied up performing various control functions.
Recent personal computers have developed bus architectures which are capable of sustaining devices which are called bus masters. A bus master may take control of the computer system at certain times and transfer data between the bus master and the system memory without requiring the service of the main or host processor. The bus master can then release the bus back to the host processor when the transfers are not necessary. In this manner, coprocessing tasks can be developed. Especially suitable for such coprocessing tasks are graphical displays, network interfacing and hard disk control subsystems. The various buses or architectures capable of supporting bus masters are exemplified by the Micro Channel Architecture (MCA) developed by International Business Machines Corporation (IBM) and the Extended Industry Standard Architecture (EISA). Thus, it became obvious to place a local processor on a separate board which could be inserted into these types of architecture for disk control functions. Intelligent disk array subsystems of this type are exemplified by the disk array controller disclosed in U.S. Pat. No. 5,206,943 for "Disk Array Controller with Parity Capabilities" assigned to Compaq Computer Corporation, assignee of the present invention, and in European Patent Office Publication No. 0427119, published Apr. 4, 1991, the counterpart to the U.S. application. The apparatus described therein utilized a disk array DMA channel composed of four individual subchannels. A dedicated XOR engine utilized one of the four subchannels, generating parity data on a word for word basis from up to four different transfer blocks. The XOR engine was also capable of writing the result to a specified drive or to a transfer buffer through the subchannel.
The use of a bus master to control disk transfer operations decreased the load on the host computer. However, the transfer of data to or from memory to the disk or disk array, or vice versa, still required time to request and complete the transfer of data. This often resulted in the host computer waiting until the disk transfer completed prior to resuming processing of the application task which requested the disk transfer. This is particularly true in the instance where the application program required information be READ from a disk to memory prior to the processor continuing execution the applications program. The reason for this idle period is apparent. If the computer attempted to READ data from memory address space to which the disk information was being transferred, prior to the completion of the transfer, the computer would READ bad or inaccurate data. Thus, computers generally waited until the transfer of data from disk to memory was complete prior to resuming execution of the applications program.
One technique long used to reduce host processor waiting times during disk transfer operations was the queued or posted WRITE technique. In WRITE operations, an active task generated a WRITE request, which was passed on to a disk device driver. The disk driver, which was special software resident on the host computer, assumed control of the system processor and generated the necessary commands to carry out WRITE operations to the disk drive or drives. During the period that the write to disk was taking place, the active process or task was in a WAIT state until the device driver received a signal from the disk controller which indicated that the WRITE operation was completed. Upon receiving the WRITE complete signal, the disk device driver software released control of the system processor and the processor resumed processing the active task.
In the posted or queued WRITE technique, the device driver directed the disk commands to a temporary queue in main memory instead of the disk controllers. A WRITE completion signal was sent by the disk driver to the processor and the disk device driver released control of the system processor to continue execution of the current task. The disk commands were then executed by the disk device driver at a later time during which a task was not active. This permitted the computer system to reduce the delay in returning to the active task.
The posted WRITE technique was also used on an intelligent disk array controller of the type exemplified in U.S. patent application Ser. No. 431,735. An active task generating a WRITE command would cause the disk device driver to assume control of the system processor. The device driver caused the system processor to generate a WRITE command list similar to that described in U.S. Pat. No. 5,249,279 assigned to Compaq computer corporation, assignee of the present invention. The WRITE command list is also described in European Patent Office Publication No. 0426184, published Mar. 27, 1991, which corresponds to U.S. Pat. No. 5,249,279. The WRITE command list may include multiple commands, including diagnostic commands, disk addresses for data to be transferred to and the number of bytes to be transferred. The WRITE command list was sent to the disk array controller and the disk device driver waited until it received a WRITE complete signal. Upon receipt of the command list, the disk array controller signaled a WRITE complete to the disk device driver, which released the system processor to resume execution of the current task. The disk array controller, including a bus master and local processor, independently carried out the WRITE commands without intervention by the system processor. Upon actual completion of the WRITE operations, the disk array controller would issue a WRITE complete confirmation signal, indicating actual completion of WRITE operations.
Therefore, WRITE operations were improved by using posted WRITE procedures. However, similar improvements have not been available for READ operations. During READ operations, the active task is conventionally waiting for the data to be returned before it can continue processing. Thus, it conventionally must wait for the full READ operation to complete before proceeding. In multitasking systems, the READ request may be a basis for a task switch, such that a different task becomes active and the requesting task is paused. While this may improve overall performance, the performance of the particular task is still reduced and may even be further reduced as a result of the task switch.